ZeqFPGA

FPGA synthesis and place-route optimization. HulyaPulse clock domain crossing verification, LUT utilization, DSP block allocation with Zeqond timing constraints.

Endpoint	POST /api/hardware/fpga
Auth	api-key
Rate limit	10/min
Category	hardware

Parameters

Name	Type	Required	Description
hdlSource	string	Yes	Verilog/VHDL source or reference.
targetDevice	string	No	FPGA family (e.g. 'xilinx-vu9p', 'intel-agilex').
constraints	object	No	Timing/pin constraints.

Returns

{ lutUtilization_pct, dspBlocks, bramUsage, fMax_MHz, timingMet, zeqond }

Example

curl -sS -X POST \
  -H "Authorization: Bearer zsm_..." \
  -H "Content-Type: application/json" \
  -d '{
  "hdlSource": "<hdlSource>",
  "targetDevice": "<targetDevice>",
  "constraints": {}
}' \
  "https://zeqsdk.com/api/hardware/fpga"

This protocol is a named building block — one of the operations you compose inside a state contract. Call it directly with the request above, or invoke it from a contract that fires on your machine's clock. Browse the whole library at GET /api/protocols; fetch this one at GET /api/protocols/zeq-fpga.